Thin film transistor panel having an etch stopper on semiconductor

ABSTRACT

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.14/798,123, filed on Jul. 13, 2015, which is a divisional of U.S. patentapplication Ser. No. 14/230,787, filed on Mar. 31, 2014, now issued asU.S. Pat. No. 9,111,805, which is a divisional of U.S. patentapplication Ser. No. 12/957,743, filed on Dec. 1, 2010, now issued asU.S. Pat. No. 8,723,179, and claims priority from and the benefit ofKorean Patent Application No. 10-2010-0012957, filed on Feb. 11, 2010,each of which is hereby incorporated by reference for all purposes as iffully set forth herein.

BACKGROUND OF THE INVENTION

Field of the Invention

Exemplary embodiments of the present invention relate to a thin filmtransistor panel and a method for fabricating a thin film transistorpanel.

Discussion of the Background

A flat panel display, such as a liquid crystal display (LCD) or anorganic light emitting display (OLED), typically includes pairs of fieldgenerating electrodes and an electro-optical active layer disposedbetween each pair of field generating electrodes.

A pixel electrode, which is one electrode of the pair of fieldgenerating electrodes, can be connected to a switching element thattransmits electrical signals to the pixel electrode. The electro-opticalactive layer operates in response to the electrical signal, therebydisplaying images.

A thin film transistor (TFT) is typically used for the switching elementthat is connected to the pixel electrode. A TFT includes a gateelectrode, a source electrode, a drain electrode, and an active layerdisposed between the gate electrode and the source electrode and thedrain electrode. The active layer may include amorphous silicon orpolycrystalline silicon.

High-mobility TFTs should be used with larger flat panel displays. A TFThaving an oxide semiconductor as an active layer has shown highperformance. The typical TFT fabrication process involves depositing andpatterning multiple layers. But when fabricating a TFT having source anddrain electrodes on an oxide semiconductor active layer, the oxidesemiconductor active layer may be damaged when forming the source andthe drain electrodes, thereby degrading the TFT's characteristics.

To reduce or prevent this damage, as disclosed in JP 2005-285890, achannel protection layer may be formed on the oxide semiconductor activelayer before forming the source and the drain electrodes. However,forming the channel protection layer on the oxide semiconductor activelayer can increase the number of photolithographic processes used tomanufacture the TFT, thereby increasing the time and cost to manufacturethe TFT panel.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a thin filmtransistor (TFT) panel in which damage to a TFT's oxide semiconductoractive layer may be reduced or prevented without increasing the numberof photolithographic processes.

Additional features of the invention will be set forth in thedescription which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention.

An exemplary embodiment of the present invention discloses a method forforming a panel including a thin film transistor. The method includesforming an oxide semiconductor pattern including a channel region,forming an etch stopper at a position corresponding to the channelregion, and forming a first electrode and a second electrode spacedapart from the first electrode. The channel region is configured toconnect the first electrode to the second electrode. The oxidesemiconductor pattern, the first electrode, and the second electrode areformed using a first mask.

An exemplary embodiment of the present invention also discloses a panelincluding a thin film transistor. The panel includes a substrate, afirst electrode on the substrate, a first insulating layer on the firstelectrode, and an oxide semiconductor pattern on the first insulatinglayer. The oxide semiconductor pattern includes a channel region. Anetch stopper is disposed on the oxide semiconductor pattern, and aconductive layer is disposed on the substrate. The conductive layerincludes a signal line, a second electrode, and a third electrode. Thesecond electrode and the third electrode are disposed on the etchstopper and the oxide semiconductor pattern. Except for the channelregion of the oxide semiconductor pattern, sidewalls of the oxidesemiconductor pattern substantially coincide with sidewalls of thesignal line, the second electrode, and the third electrode.

An exemplary embodiment of the present invention also discloses a methodfor forming a panel including a thin film transistor. The methodincludes forming an oxide semiconductor pattern including a channelregion, forming an etch stopper at a position corresponding to thechannel region, and forming a first electrode and a second electrodespaced apart from the first electrode. The channel region is configuredto connect the first electrode to the second electrode. The etch stopperand the oxide semiconductor pattern are formed using a first mask.

An exemplary embodiment of the present invention also discloses a panelincluding a thin film transistor. The panel includes a substrate, afirst electrode on the substrate, a first insulating layer on the firstelectrode, an oxide semiconductor pattern on the first insulating layer,an etch stopper on the oxide semiconductor pattern, and a secondelectrode and a third electrode on the etch stopper and the oxidesemiconductor pattern. The first insulating layer includes a firstregion disposed under the etch stopper and a second region disposedoutside the first region. A thickness of the first region differs from athickness of the second region.

An exemplary embodiment of the present invention also discloses a panelincluding a thin film transistor. The panel includes a substrate, afirst electrode on the substrate, a first insulating layer on the firstelectrode, an oxide semiconductor pattern on the first insulating layer,an etch stopper on the oxide semiconductor pattern, and a secondelectrode and a third electrode on the etch stopper and the oxidesemiconductor pattern. A pattern of the etch stopper is containedentirely within a perimeter of the oxide semiconductor pattern, anddistances between corresponding sidewalls of the etch stopper and theoxide semiconductor pattern are substantially the same.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention, andtogether with the description serve to explain the principles of theinvention.

FIG. 1 is a plan view of a thin film transistor (TFT) panel according toan exemplary embodiment the present invention.

FIG. 2A is a cross-sectional view taken along line A-A′ of FIG. 1.

FIG. 2B is a cross-sectional view taken along line B-B′ of FIG. 1.

FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are cross-sectional views showingsteps for manufacturing the TFT panel of FIG. 1 according to anexemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of a TFT panel according to anexemplary embodiment of the present invention.

FIG. 8 is a plan view of a TFT panel according to an exemplaryembodiment of the present invention.

FIG. 9 is a cross-sectional view taken along line C-C′ of FIG. 8.

FIG. 10, FIG. 11, FIG. 12, FIG. 13, and FIG. 14 are cross-sectionalviews showing steps for manufacturing the TFT panel of FIG. 8 accordingto an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Exemplary embodiments of the present invention now will be describedmore fully hereinafter with reference to the accompanying drawings. Thisinvention may, however, be embodied in many different forms and shouldnot be construed as limited to the exemplary embodiments set forthherein. Rather, these exemplary embodiments are provided so that thisdisclosure is thorough, and will fully convey the scope of the inventionto those skilled in the art. Like reference numerals refer to likeelements throughout.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “connected to” another element or layer,it can be directly on, connected or connected to the other element orlayer or intervening elements or layers may be present. In contrast,when an element is referred to as being “directly on,” “directlyconnected to” or “directly connected to” another element or layer, thereare no intervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particularexemplary embodiments only and is not intended to be limiting of theinvention. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” or “includes” and/or “including” whenused in this specification, specify the presence of stated features,regions, integers, steps, operations, elements, and/or components, butdo not preclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toother elements as illustrated in the Figures. It will be understood thatrelative terms are intended to encompass different orientations of thedevice in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower”, can therefore, encompasses both an orientation of “lower” and“upper,” depending on the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Exemplary embodiments of the present invention are described herein withreference to cross section illustrations that are schematicillustrations of idealized embodiments of the present invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the present invention should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, a region illustrated or described asflat may, typically, have rough and/or nonlinear features. Moreover,sharp angles that are illustrated may be rounded. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region and are notintended to limit the scope of the present invention.

All methods described herein can be performed in a suitable order unlessotherwise indicated herein or otherwise clearly contradicted by context.The use of any and all examples, or exemplary language (e.g., “suchas”), is intended merely to better illustrate the exemplary embodimentsof the invention and does not pose a limitation on the scope of theinvention unless otherwise claimed. No language in the specificationshould be construed as indicating any non-claimed element as essentialto the practice of the invention as used herein.

Hereinafter, exemplary embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a thin film transistor (TFT) panel 1 accordingto an exemplary embodiment the present invention. FIG. 2A is across-sectional view taken along line A-A′ of FIG. 1, and FIG. 2B is across-sectional view taken along line B-B′ of FIG. 1. While only asingle pixel of the TFT panel 1 is shown in FIG. 1, one of ordinaryskill in the art may appreciate that the TFT panel 1 may have multiplepixels, and according to an exemplary embodiment of the presentinvention, they may be disposed in a matrix on the TFT panel 1.

Referring to FIG. 1, FIG. 2A, and FIG. 2B, multiple gate lines 22 andstorage electrode lines 28 are formed on an insulating substrate 10. Theinsulating substrate 10 may be made of glass, plastic, or other suitableinsulating materials.

The gate lines 22, which extend in a first direction, transmit gatesignals. Each gate line 22 includes gate electrodes 24 that protrudefrom the gate line 22 and a gate pad (not shown). A driving circuit,such as a gate driving circuit, applies driving signals to the gate pad.Alternatively, the gate pad may be omitted and the gate lines 22 mayreceive driving signals from a driving circuit disposed on the substrate10.

The storage electrode lines 28 extend parallel with the gate lines 22.Each storage electrode line 28 includes storage electrodes 29 thatprotrude from the storage electrode line 28. The storage electrodes 29are arranged parallel with a corresponding data line 62. The storageelectrode 29 includes an opening in its central portion. Thus, thestorage electrode 29 may have a tetragonal ring shape. In this case, aportion of the opening may be disposed to overlap with the data line 62.The storage electrode line 28 may receive a preset voltage. The storageelectrode lines 28 and the storage electrodes 29 can have various shapesand arrangements. Alternative exemplary embodiments also includeconfigurations in which the storage electrode lines 28 are omitted.

The gate lines 22 and the storage electrode lines 28 can be made ofvarious conductive materials. For example, the gate lines 22 and thestorage electrode lines 28 can include aluminum (Al) or an aluminumalloy, silver (Ag) or a silver alloy, copper (Cu) or a copper alloy,molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), andtitanium (Ti). According to an exemplary embodiment, the gate lines 22and the storage electrode lines 28 can include multiple layers made ofvarious conductive materials. For example, they may include adouble-layered structure such Al and Mo or Ti and Cu.

A gate insulating layer 30 is formed on the insulating substrate 10, thegate lines 22, and the storage electrode lines 28. The gate insulatinglayer 30 can include an insulating material such as silicon nitride(SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or otherappropriate insulating materials. The gate insulating layer 30 caninclude multiple layers made of various insulating materials. Forexample, the gate insulating layer 30 can include a double-layeredstructure of a lower layer of SiNx and an upper layer of SiOx.

An oxide semiconductor layer 42, which includes a channel region of aTFT, is formed on the gate insulating layer 30. The effective carriermobility of an oxide semiconductor may be two to one hundred timesgreater than that of amorphous silicon. The oxide semiconductor layer 42may include one or more compounds represented by the formulasA_(X)B_(X)O_(X) and A_(X)B_(X)C_(X)O_(X). Here, A may be In, Zn, Ga, Hf,or Cd; B may be Zn, Ga, Sn, or In; C may be Sn, Zn, Cd, Ga, In, or Hf;and O is atomic oxygen. Each x is independently a non-zero integer, andA, B, and C are different from one another. For example, the oxidesemiconductor layer 42 can include one or more of the followingcompounds: InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, GaInZnO,and HfInZnO.

An etch stopper 52 is formed on the oxide semiconductor layer 42. Theetch stopper 52 covers the channel region of the oxide semiconductorlayer 42, thereby preventing or reducing damage to the channel regioncaused by an etching solution, an etching gas, or plasma used during asubsequent manufacturing process. The etch stopper 52 may be made of aninsulating material. For example, the etch stopper 52 may be made ofSiOx, SiNx or other appropriate insulating materials. Generally, thechannel region refers to a portion of a semiconductor layer that forms acurrent path between a source electrode and a drain electrode.

Multiple data lines 62 and drain electrodes 66 are formed on the gateinsulating layer 30, the oxide semiconductor layer 42, and the etchstopper 52. The data lines 62 transmit data signals and extend in asecond direction crossing the gate lines 22. Each data line 62 includessource electrodes 65 that protrude toward corresponding gate electrodes24. The drain electrode 66 is disposed opposite to and spaced apart fromthe corresponding source electrode 65 with respect to the gate electrode24. A portion of the oxide semiconductor layer 42 between the sourceelectrode 65 and the drain electrode 66 forms the TFT's channel.

The source electrode 65 and the drain electrode 66 may be formed onsidewalls of the etch stopper 52, as well as on a portion of a topsurface of the etch stopper 52 that extends from the sidewalls. As notedabove, the source electrode 65 is spaced apart from the drain electrode66. Thus, the source electrode 65 and the drain electrode 66 expose aportion of the top surface of the etch stopper 52.

As described in detail below, the data line 62, source electrode 65,drain electrode 66, and oxide semiconductor layer 42 may be formed usingthe same mask. Consequently, except for the portion of the oxidesemiconductor layer 42 between the source and drain electrodes 65 and 66(i.e., the channel region), the oxide semiconductor layer 42 can havesubstantially the same shape as the data line 62, source electrode 65,and drain electrode 66. In this case, the data line 62, source electrode65, and drain electrode 66 are not disposed directly on sidewalls of theoxide semiconductor layer 42. Further, because the same mask is used, asFIG. 2A shows, the sidewalls of the oxide semiconductor layer 42, exceptfor the channel region, substantially coincide with the sidewalls of thedata line 62, source electrode 65, and drain electrode 66. Furthermore,as FIG. 2B shows, sidewalls of the channel region of the oxidesemiconductor layer 42 substantially coincide with sidewalls of the etchstopper 52.

Although FIG. 2A shows sidewalls of the oxide semiconductor layer 42formed along the same line as the sidewalls of the data line 62, sourceelectrode 65, and drain electrode 66, the actual manufacturing processwill likely not produce such alignment. For example, because of thematerials and etchants used to manufacture the TFT panel 1, thesidewalls may be curved or not formed in the same line. Thus, for thesidewalls to “substantially coincide with” each other as described here,it is not necessary for the sidewalls be formed along the same line asshown in FIG. 2A. Rather, as noted above, the sidewalls of the oxidesemiconductor layer 42 substantially coincide with the sidewalls of thedata line 62, source electrode 65, and drain electrode 66 because thesame mask is used to form these elements. Similarly, although FIG. 2Bshows sidewalls of the channel region of the oxide semiconductor layer42 formed along the same line as the sidewalls of the etch stopper 52,the actual manufacturing process will likely not produce such alignment.Thus, for the sidewalls to “substantially coincide with” each other asdescribed here, it is not necessary for the sidewalls be formed alongthe same line as shown in FIG. 2B. Rather, sidewalls of the channelregion of the oxide semiconductor layer 42 substantially coincide withsidewalls of the etch stopper 52 because the etch stopper 52 masks thechannel region during the process of patterning the oxide semiconductorfilm 40.

If the work function of the data line 62, source electrode 65, and drainelectrode 66 is lower than that of the oxide semiconductor layer 42, thedata line 62, source electrode 65, and drain electrode 66 can be formeddirectly on the oxide semiconductor layer 42 to form an ohmic contact.

The data line 62, source electrode 65, and the drain electrode 66 caninclude various conductive materials. For example, they may includenickel (Ni), cobalt (Co), titanium (Ti), silver (Ag), copper (Cu),molybdenum (Mo), aluminum (Al), beryllium (Be), niobium (Nb), gold (Au),iron (Fe), selenium (Se), tantalum (Ta), zirconium (Zr), tungsten (W),platinum (Pt), hafnium (Hf), or an alloy thereof. Further, the data line62, source electrode 65, and drain electrode 66 can include oxygen (O)or nitrogen (N).

The data line 62, source electrode 65, and drain electrode 66 can have amultiple layered structure. For example, the data line 62, sourceelectrode 65, and drain electrode 66 can have a double-layered structureincluding a lower layer and an upper layer. In this case, the lowerlayer can include titanium (Ti), titanium nitride (TiNx), a copper alloysuch as copper manganese (CuMn), or other materials having similarcharacteristics, and the upper layer can include copper (Cu) or a copperalloy or other material having similar characteristics. In anotheralternative, the data line 62, source electrode 65, and drain electrode66 can have a multi-layered structure including a lower molybdenum (Mo)layer, an aluminum (Al) layer on the lower Mo layer, and an upper Molayer on the Al layer, or other appropriate conductive materials.

A passivation layer 70 is disposed on the etch stopper 52, the data line62, the source electrode 65, the drain electrode 66, and the gateinsulating layer 30. The passivation layer 70 can include an insulatingmaterial such as silicon oxide (SiOx), silicon nitride (SiNx), siliconoxynitride (SiON), or other appropriate insulating materials. Thepassivation layer 70 may include multiple layers. For example, thepassivation layer 70 can include a double-layered structure of SiOx andSiNx. Further, the passivation layer 70 can also include an organiclayer instead of or in addition to an inorganic layer.

A pixel electrode 80 is disposed on the passivation layer 70 andconnected to the drain electrode 66 through the contact hole 75. Thepixel electrode 80 can include a transparent conductive material such asindium tin oxide (ITO) and indium zinc oxide (IZO).

FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are cross-sectional views showingsteps for manufacturing the TFT panel 1 of FIG. 1 according to anexemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 3, a gate conductive layer (not shown) isformed on an insulating substrate 10, e.g. by sputtering, and patternedusing a photolithographic process to form a gate line 22, gate electrode24, storage electrode line 28, and storage electrode 29. A dry etchprocess or a wet etch process can be used to pattern the gate conductivelayer. If the gate conductive layer is wet etched, etchant such asphosphoric acid, nitric acid, and acetic acid can be used. If the gateconductive layer is dry etched, chlorine based gas such as Cl₂ and BCl₃can be used.

The insulating substrate 10 can include glass, such as soda lime glassand boron silicate glass, or plastic. The gate conductive layer caninclude a double-layered structure such as Al and Mo, or Ti and Cu orother appropriate conductive materials.

Referring to FIG. 1 and FIG. 4, a gate insulating layer 30 is formed,e.g. by chemical vapor deposition (CVD), on the gate line 22 and thestorage electrode line 28. An oxide semiconductor film 40 is formed,e.g. by sputtering, on the gate insulating layer 30, and an etch stopperlayer (not shown) is formed, e.g. by CVD, on the oxide semiconductorfilm 40. The etch stopper layer may be patterned using aphotolithographic process to form an etch stopper 52. The etch stopperlayer may be patterned using a dry etch process. The dry etch processcan be performed using at least one of CF₃, CHF₆, and Cl₂ as etchinggases.

Referring to FIG. 1 and FIG. 5, a data conductive layer (not shown) isformed, e.g. by sputtering, on the etch stopper 52 and the oxidesemiconductor film 40. The data conductive layer and the oxidesemiconductor film 40 may be patterned using a photolithographic processand a single mask, thereby forming a data line 62, which includes asource electrode 65, a drain electrode 66, and an oxide semiconductorlayer 42. The source electrode 65 and the drain electrode 66 are spacedapart from each other with respect to the gate electrode 24. A portionof the etch stopper 52 between the source electrode 65 and the drainelectrode 66 is exposed, and the source electrode 65 and the drainelectrode 66 cover a portion of the top surface and sidewalls of theetch stopper 52.

The data conductive layer and the oxide semiconductor film 40 may bepatterned using a wet etch process. In this case, the etch stopper 52and the gate insulating layer 30 may be resistant to, and thus notdamaged by, chemicals used in the wet etch process. Accordingly, theetch stopper 52 can protect the underlying oxide semiconductor layer 42from damage from chemicals.

As noted above, the data conductive layer and the oxide semiconductorfilm 40 may be patterned using a single mask. Consequently, except forthe portion between the source and drain electrodes 65 and 66 (i.e., thechannel region), the oxide semiconductor layer 42 can have substantiallythe same shape as the data line 62, source electrode 65, and drainelectrode 66. Thus, in this case, as FIG. 2A shows, the data line 62,source electrode 65, and drain electrode 66 are not disposed directly onsidewalls of the oxide semiconductor layer 42. Further, because the samemask is used to pattern the data conductive layer and the oxidesemiconductor film 40, except for the channel region, the sidewalls ofthe oxide semiconductor layer 42 substantially coincide with thesidewalls of the data line 62, source electrode 65, and drain electrode66. Furthermore, as FIG. 2B shows, sidewalls of the channel region ofthe oxide semiconductor layer 42 substantially coincide with sidewallsof the etch stopper 52 because the etch stopper 52 masks the channelregion during the process of patterning the data conductive layer andthe oxide semiconductor film 40.

Referring to FIG. 6, a passivation layer 70 is formed, e.g. by CVD, onthe data line 62, the source electrode 65, the drain electrode 66, theetch stopper 52, and the gate insulating layer 30 and then patterned toform a contact hole 75. The contact hole 75 exposes a portion of thedrain electrode 66. The contact hole may alternatively expose a portionof the source electrode 65.

Referring to FIG. 2A, a transparent conductive layer is formed on thepassivation layer 70 and patterned to form a pixel electrode 80. Thepixel electrode 80 may be connected to the drain electrode 66 throughthe contact hole 75.

Although FIG. 2A shows a TFT having a bottom gate structure, in whichthe gate electrode 24 is disposed under the oxide semiconductor layer42, other structures are possible. For example, the TFT may have a topgate structure, in which the gate electrode is disposed on the oxidesemiconductor layer.

FIG. 7 is a cross-sectional view of a TFT panel according to anexemplary embodiment of the present invention.

The exemplary embodiment of the TFT panel shown in FIG. 7 issubstantially identical to the exemplary embodiment shown in FIG. 1 andFIG. 2A except that the passivation layer 70 is replaced with colorfilters 71R and 71G.

Referring to FIG. 7, a TFT panel 1 a includes a gate insulating layer30, an oxide semiconductor layer 42, and an etch stopper 52. A sourceelectrode 65 and a drain electrode 66 are disposed on the oxidesemiconductor layer 42 and the etch stopper 52. The etch stopper 52prevents the portion of the oxide semiconductor layer 42 between thesource electrode 65 and the drain electrode 66 from being exposed,thereby protecting the oxide semiconductor layer 42 from damage duringan etching process. Accordingly, even though color filters 71R and 71Gare formed instead of the passivation layer 70, the oxide semiconductorlayer 42 can be protected. The red color filter 71R may overlap with thegreen color filter 71G near where the data line 62 is disposed on aportion 43 of the oxide semiconductor layer. As another alternative, anorganic film can be formed on the substrate including the TFT instead ofcolor filters 71R and 71G.

FIG. 8 is a plan view of a TFT panel 1 b according to an exemplaryembodiment of the present invention, and FIG. 9 is a cross-sectionalview taken along line C-C′ of FIG. 8. This exemplary embodiment of theTFT panel 1 b is substantially the same as the exemplary embodimentshown in FIG. 1 except for the configuration of an oxide semiconductorlayer and an etch stopper. In this exemplary embodiment, the oxidesemiconductor layer and the etch stopper are formed using the same mask.The same reference numerals will be used to refer to the same or likeparts as those described in the exemplary embodiment of FIG. 1, and anyfurther explanation will be omitted.

Referring to FIG. 1, FIG. 2A, and FIG. 2B, except for its channelregion, the oxide semiconductor layer 42 can have substantially the sameshape as the data line 62, source electrode 65, and drain electrode 66.Thus, the sidewalls of the data line 62, source electrode 65, and drainelectrode 66 substantially coincide with the sidewalls of the oxidesemiconductor layer 42, except for the channel region. Further, as FIG.2A shows, the data line 62, source electrode 65, and drain electrode 66are not disposed directly on sidewalls of the oxide semiconductor layer42. On the other hand, referring to FIG. 8 and FIG. 9, a sourceelectrode 65 and a drain electrode 66 cover at least one sidewall of anoxide semiconductor layer 42 a. Further, an etch stopper 52 a may havesubstantially the same shape as the oxide semiconductor layer 42 a. Atleast one sidewall of the etch stopper 52 a is disposed inside theperimeter of the oxide semiconductor layer 42 a, thus permitting thesource electrode 65 and the drain electrode 66 to be formed directly ona portion of a top surface of the oxide semiconductor layer 42 a.

Referring to FIG. 8, because the oxide semiconductor layer 42 a and theetch stopper 52 a are formed using the same mask, the oxidesemiconductor layer 42 a and the etch stopper 52 a may havesubstantially the same shape. Further, sidewalls of the etch stopper 52a are disposed inside the perimeter of the oxide semiconductor layer 42a. In other words, a pattern of the etch stopper 52 a may be containedentirely within a perimeter of the oxide semiconductor layer 42 a.Furthermore, as the enlarged portion contained within the broken circleof FIG. 8 shows, because the same mask is used to form the etch stopper52 a and the oxide semiconductor 42 a, the distances “d” betweencorresponding sidewalls of the oxide semiconductor layer 42 a and theetch stopper 52 a may be substantially the same.

In an alternative exemplary embodiment of the present invention, theetch stopper 52 a can be narrower than the oxide semiconductor layer 42a along the direction parallel with a gate line 22, like shown in FIG.8. But unlike FIG. 8, the etch stopper 52 a may be wider than andcompletely cover the oxide semiconductor layer 42 a along the directionparallel with a data line 62, thereby protecting more of the oxidesemiconductor layer 42 a.

FIG. 10, FIG. 11, FIG. 12, FIG. 13, and FIG. 14 are cross-sectionalviews showing steps for manufacturing the TFT panel 1 b of FIG. 8according to an exemplary embodiment of the present invention.

Referring to FIG. 8 and FIG. 10, a gate conductive layer (not shown) isformed on an insulating substrate 10, e.g. by sputtering, and patternedusing a photolithographic process to form a gate line 22, gate electrode24, storage electrode line 28, and storage electrode 29. A dry etchprocess or a wet etch process can be used to pattern the gate conductivelayer. If the gate conductive layer is wet etched, etchant such asphosphoric acid, nitric acid, and acetic acid can be used. If the gateconductive layer is dry etched, chlorine based gas such as Cl₂ and BCl₃can be used.

The insulating substrate 10 can include glass, such as soda lime glassand boron silicate glass, or plastic. The gate conductive layer caninclude a double-layered structure such as Al and Mo, or Ti and Cu orother appropriate conductive materials.

A gate insulating layer 30 is formed, e.g. by CVD, on the gate line 22and the storage electrode line 28. An oxide semiconductor film 40 isformed, e.g. by sputtering, on the gate insulating layer 30, and an etchstopper layer 50 is formed, e.g. by CVD, on the oxide semiconductor film40.

Referring to FIG. 8 and FIG. 11, a photo-resist layer (not shown) isformed on the etch stopper layer 50 and patterned to form a photo-resistpattern 99 a. The etch stopper layer 50 having the photo-resist pattern99 a thereon may then be etched to form an interim etch stopper 51.Here, the etch stopper layer 50 may be etched using a dry etch process.A halogen based gas, such as CF₆, CHF₆, and Cl₂, can be used in the dryetch process.

After forming the interim etch stopper 51, the oxide semiconductor film40 having the photo-resist pattern 99 a and the interim etch stopper 51thereon may be etched to form an oxide semiconductor layer 42 a. Here,the oxide semiconductor film 40 may be etched using a wet etch process.Etchant such as phosphoric acid, nitric acid, and acetic acid can beused in the wet etch process.

Because the wet etch process may be an isotropic etch process, it formsan undercut U under the interim etch stopper 51. Thus, the oxidesemiconductor layer 42 a is narrower than the interim etch stopper 51.

Referring to FIG. 12, the interim etch stopper 51 is etched to form anetch stopper 52 a. Thus, per the above description and as shown in FIG.10, FIG. 11, and FIG. 12, the oxide semiconductor layer 42 a and theetch stopper 52 a may be formed using a single mask (i.e., the mask usedto form the photo-resist pattern 99 a from the photo-resist layer (notshown)). Further, because the oxide semiconductor layer 42 a and theetch stopper 52 a are formed using a single mask and the etchingprocesses described above, all sidewalls of the etch stopper 52 a may bedisposed inside the oxide semiconductor layer 42 a. In other words, apattern of the etch stopper 52 a may be contained entirely within aperimeter of the oxide semiconductor layer 42 a. Furthermore, as theenlarged portion contained within the broken circle of FIG. 8 shows,because the same mask is used to form the etch stopper 52 a and theoxide semiconductor 42 a, the distances “d” between correspondingsidewalls of the oxide semiconductor layer 42 a and the etch stopper 52a may be substantially the same. This configuration increases thecontact areas between the oxide semiconductor layer 42 a and the sourceand drain electrodes 65 and 66 (shown in FIG. 8 and FIG. 13).

Here, the interim etch stopper 51 may be dry etched to form the etchstopper 52 a. A gas mixture of SF₆ and Cl₂ can be used for the dry etchprocess. During the dry etch process, a portion of the gate insulatinglayer 30 and a portion of the photo-resist pattern 99 a may be removed,thereby forming a gate insulating layer 32 and a smaller photo-resistpattern 99 b.

Because a portion of the gate insulating layer 30 may be removed duringthe dry etch process, the gate insulating layer 32 can include a stepportion in the area overlapping with the oxide semiconductor layer 42 a.In other words, unlike gate insulating layer 30 (i.e., the non-etchedgate insulating layer), gate insulating layer 32 (i.e., the etched gateinsulating layer) includes regions with different thicknesses.Specifically, as FIG. 12 shows, the region of the gate insulating layer32 disposed under the oxide semiconductor 42 a and etch stopper 52 a isthicker than the other regions of the gate insulating layer 32. Here,the region of the gate insulating layer 32 disposed under the oxidesemiconductor 42 a and etch stopper 52 a is thicker than the otherregions because this region is not etched during the dry etch process.

Alternatively, a half tone mask or a slit mask can be used to form theetch stopper 52 a and the oxide semiconductor layer 42 a. The half tonemask or the slit mask has a portion through which light partiallytransmits, thereby adjusting an amount of light irradiated on theunderlying substrate. Specifically, a photo-resist layer may be formedon the etch stopper layer 50 of FIG. 10. The photo-resist layer is thenexposed to light with the half tone mask or the slit mask, which wouldbe disposed over the photo-resist layer. Light is blocked in the area ofthe photo-resist layer corresponding to the etch stopper 52 a of FIG.12, and the photo-resist layer remains with a determined thickness aftera developing process. In the area of the photo-resist layercorresponding to the edges of the interim etch stopper 51 of FIG. 11,light partially transmits through the mask and a thinner photo-resistlayer than the determined thickness is formed after the developingprocess. In the other area of the photo-resist layer, light fullytransmits through the mask, and that area of the photo-resist layer iscompletely removed after the developing process. As a result, aphoto-resist pattern having different thickness depending on the area isformed. The etch stopper layer 50 and the oxide semiconductor 40 havingthe photo-resist pattern thereon may then be etched, thereby forming theetch stopper 52 a and the oxide semiconductor layer 42 a with the samestructure shown in FIG. 12.

Referring to FIG. 8 and FIG. 13, a data conductive layer (not shown) isformed, e.g. by sputtering, on the etch stopper 52 a and the oxidesemiconductor layer 42 a. The data conductive layer may be patternedusing a photolithographic process to form a data line 62, which includesa source electrode 65, and a drain electrode 66. The source electrode 65and the drain electrode 66 are spaced apart from each other with respectto the gate electrode 24. A portion of the etch stopper 52 a between thesource electrode 65 and the drain electrode 66 is exposed. Further, thesource electrode 65 and the drain electrode 66 are formed on a portionof a top surface and sidewalls of the etch stopper 52 a. Also, thesource electrode 65 and the drain electrode 66 are formed on sidewallsand a portion of a top surface extending from the sidewalls of the oxidesemiconductor layer 42 a.

The data conductive layer may be patterned using a wet etch process.Here, the etch stopper 52 a and the gate insulating layer 32 may beresistant to, and thus not damaged by, chemicals used in the wet etchprocess. Accordingly, the etch stopper 52 a can protect the underlyingoxide semiconductor layer 42 a from damage from chemicals.

Referring to FIG. 14, a passivation layer 70 is formed, e.g. by CVD, onthe data line 62, the source electrode 65, the drain electrode 66, theetch stopper 52 a, and the gate insulating layer 32 and then patternedto form a contact hole 75. The contact hole 75 exposes a portion of thedrain electrode 66. The contact hole may alternatively expose a portionof the source electrode 65.

Referring to FIG. 9, a transparent conductive layer is formed on thepassivation layer 70 and patterned to form a pixel electrode 80. Thepixel electrode 80 may be connected to the drain electrode 66 throughthe contact hole 75.

According to exemplary embodiments of the present invention, an etchstopper can be formed to protect an oxide semiconductor layer fromdamage resulting from a subsequent manufacturing process withoutincreasing processing steps. Also, sidewalls of the etch stopper may bedisposed within the perimeter of the oxide semiconductor layer, therebyincreasing the contact area between the oxide semiconductor layer andsource and drain electrodes.

It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A method for forming a panel comprising a thinfilm transistor, the method comprising: forming an oxide semiconductorpattern comprising a channel region; forming an etch stopper at aposition corresponding to the channel region; and forming a firstelectrode and a second electrode spaced apart from the first electrode,the channel region configured to connect the first electrode to thesecond electrode, wherein the etch stopper and the oxide semiconductorpattern are formed using a first mask.
 2. The method of claim 1, furthercomprising: disposing a first conductive layer on a substrate; disposinga first insulating layer on the first conductive layer; disposing anoxide semiconductor layer on the first insulating layer; and disposingan etch stop layer on the oxide semiconductor layer; wherein the etchstopper and the oxide semiconductor pattern are formed by patterning theetch stop layer and the oxide semiconductor layer using the first mask.3. The method of claim 2, wherein patterning the etch stop layer and theoxide semiconductor layer comprises forming a photoresist pattern usingthe first mask.
 4. The method of claim 3, wherein patterning the etchstop layer and the oxide semiconductor layer further comprises etchingthe etch stop layer having the photoresist pattern thereon to form aninterim etch stopper.
 5. The method of claim 4, wherein patterning theetch stop layer and the oxide semiconductor layer further comprisesetching the oxide semiconductor layer having the interim etch stopperthereon to form the oxide semiconductor pattern.
 6. The method of claim5, wherein patterning the etch stop layer and the oxide semiconductorlayer further comprises etching the interim etch stopper to form theetch stopper.
 7. The method of claim 6, wherein the interim etch stopperis formed by dry etching the etch stop layer.
 8. The method of claim 7,wherein the oxide semiconductor pattern is formed by wet etching theoxide semiconductor layer.
 9. The method of claim 8, wherein the etchstopper is formed by dry etching the interim etch stopper.
 10. Themethod of claim 9, wherein etching the interim etch stopper to form theetch stopper further comprises etching the first insulating layer. 11.The method of claim 6, further comprising: forming a second conductivelayer on the etch stopper and the oxide semiconductor pattern, whereinthe second conductive layer is patterned to form the first electrode andthe second electrode.
 12. The method of claim 11, further comprising:forming a second insulating layer on the first electrode and the secondelectrode; patterning the second insulating layer to form a contact holeexposing the first electrode; and forming a third conductive layer onthe second insulating layer; patterning the third conductive layer toform a third electrode, wherein the third electrode is connected to thefirst electrode via the contact hole.
 13. The method of claim 12,wherein the second insulating layer comprises a passivation layer. 14.The method of claim 12, wherein the second insulating layer comprises acolor filter.
 15. The method of claim 12, further comprising: patterningthe first conductive layer to form a fourth electrode, the fourthelectrode being disposed under the etch stopper and the oxidesemiconductor pattern.
 16. The method of claim 15, wherein the firstconductive layer is patterned using a second mask, the second conductivelayer is patterned using a third mask, the second insulating layer ispatterned using a fourth mask, and the third conductive layer ispatterned using a fifth mask.